The present invention relates to a device for controlling a clock signal phase, and more particularly to a device for controlling a clock signal phase difference between two chips to reduce clock skew.
While an integrated circuit chip is operating, it is desirable to synchronize the operation clock signals for circuits inside and outside the chip in order to avoid confusion of control signals and thus invalidation of the chip. However, there are many factors that may result in a clock skew problem. For example, a pad circuit which functions as an input/output buffer in a chip, the parasitic capacitance of an external circuit responsive to the clock signal, and the unpredicted operational temperature may be factors resulting in clock delay. Unfortunately, these factors cannot keep under control by the chip designer. Thus, it becomes an important issue for the chip designer to compensate the clock delay effect in order to avoid clock skew.
FIG. 1 is a functional block diagram schematically showing a conventional device for controlling a clock signal phase difference between an internal and an external circuits of a chip. As shown in FIG. 1, a typical chip includes a phase-locked loop (PLL) clock signal generator 10, a pad circuit 12 and a clock tree 13. A clock signal generated by the PLL clock signal generator 10 is transmitted out to another chip 19 via the pad circuit 12. The clock tree 13 is used to synchronize the clock signals received by different elements in the same chip. For controlling a clock signal phase difference between an output end 121 of the pad circuit 12 and an output end 131 of the clock tree 13, a data precision adjustment (DPA) device 11 is disposed between the PLL clock signal generator 10 and the pad circuit 12. The data precision adjustment device 11 is used for adjusting a clock signal phase of the output end 121 of the pad circuit 12. Ideally, the phase difference between the clock signal outputted from the output end 121 of the pad circuit 12 into the chip 19 and the clock signal outputted from the output end 131 of the clock tree 13 is zero. Unfortunately, the clock signal transmitted out from the pad circuit 12 is inherently delayed to an extent, and the loading of the trace on the circuit board between the output end 121 of the pad circuit 12 and the chip 19 is hard to be controlled. Hence, when the trace on the circuit board is changed, it is necessary for the data precision adjustment device 11 to perform another adjusting operation due to the altered loading. It is troublesome for the designer and the producer.
Please refer to FIG. 2 which is a functional block diagram illustrating another conventional clock-signal-phase control device. A clock signal generated from a phase-locked loop (PLL) clock signal generator 20 is processed by a clock tree 21 and a first data precision adjustment (DPA) device 22, and transmitted to a deskew PLL clock signal generator 23 as a reference signal. Then, the clock signal outputted from the deskew PLL clock signal generator 23 is transmitted to another chip 29 via a first pad circuit 24 and a circuit board trace 25. For precisely realizing a phase shift situation of the clock signal received by an input end 291 of the chip 29, a feedback signal is picked from a point M which is a half of the length 2L of the circuit board trace 25 distant from said input end 291, and transmitted back to an input end 261 of a second pad circuit 26 in the original chip via a feedback trace whose length is L. Under this circumstance, the connecting trace length from the first pad circuit 24 to the input end 291 of the chip 29 is equal to the feedback trace length from the first pad circuit 24 to the input end 261 of the second pad circuit 26, both being 2L. Hence, the phase shift of the input end 291 of the external chip 29 is expected to be the same as that of the input end 261 of a second pad circuit 26. The feedback signal is then processed by the second pad circuit 26 and a second data precision adjustment device 27, and transmitted to the deskew PLL clock signal generator 23 to be phase-locked, thereby eliminating the phase difference between the reference signal and the feedback signal. The clock skew problem can thus be efficiently solved. In this conventional control device, however, additional devices such as the deskew PLL clock signal generator 23 and the second pad circuit 26 are required to perform a feedback operation. As known, these additional devices will occupy some area of the chip and increase the production cost. Furthermore, with the increasingly rising of the working clock frequency, the design of the deskew PLL clock signal generator becomes more and more complicated and difficult.
Therefore, the purpose of the present invention is to develop a device for controlling a clock signal phase to deal with the above situations encountered in the prior art.
An object of the present invention is to provide a device for controlling a clock signal phase for use in a structure that a first chip outputs a clock signal to a second chip via an external circuit for reducing the clock skew.
Another object of the present invention is to provide a device for controlling a clock signal phase for use in a structure that a first chip outputs a clock signal to a second chip via an external circuit for improving the stability of the clock signal phase difference.
A further object of the present invention is to provide a device for controlling a clock signal phase for use in a structure that a first chip outputs a clock signal to a second chip via an external circuit for reducing the cost and the occupied area of the chip.
According to an aspect of the present invention, there is provided a device for controlling a clock signal phase for use in a structure that a first chip outputs a clock signal to a second chip via an external circuit. The device includes a clock signal generator disposed in the first chip for generating the clock signal, a pad circuit disposed in the first chip, electrically connected between the clock signal generator and the external circuit, and including an output buffer and an input buffer, wherein the output buffer transmits the clock signal to both of the external circuit and the input buffer, and the input buffer further transmits the clock signal to a logic circuit module of the first chip, and a phase adjustment device disposed in the first chip and electrically connected between an output end of the input buffer and the logic circuit module of the first chip for adjusting the clock signal required for the operation of the logic circuit module. For example, the external circuit can be a connecting trace, and the clock signal generator can be of a phase-locked loop (PLL) type.
Preferably, the phase adjustment device includes a clock tree electrically connected to the logic circuit module for delaying the clock signal received thereby by a preset time, and a data precision adjustment device electrically connected between the output end of the input buffer and an input end of the clock tree for compensating the clock signal received thereby to eliminate a clock signal phase difference between the logic circuit module and the output end of the input buffer.
According to another aspect of the present invention, the control device includes a clock signal generator disposed in the first chip for generating the clock signal, and a pad circuit electrically connected between the clock signal generator and the external circuit and including an output buffer and an input buffer. The output buffer transmits the clock signal to both of the external circuit and the input buffer, and the input buffer further transmits the clock signal to a logic circuit module of the first chip for the operation of the logic circuit module.